1. Field of the Invention
The present invention generally relates to a gate driving circuit, and more particularly, to a power control circuit adapted for protecting a gate driving circuit.
2. Description of Related Art
Gate driving circuits are known as critical components of thin film transistor liquid crystal displays (TFT-LCDs). In a TFT-LCD, a gate driving circuit is responsible for turning on/off TFTs on each row of pixels in the TFT-LCD panel. In order to avoid burning suddenly of the gate driving circuit, a typical approach is to delay the input timing of a partial power inputting to the gate driving circuit for a certain amount.
FIG. 1 is a block diagram illustrating a conventional approach for protecting a gate driving circuit. Referring to FIG. 1, a power supply 11 is employed for outputting a first power VDDG and a second power VEEG. The first power VDDG is adapted for providing a voltage level to a gate driving circuit 13 for controlling each row of pixels in the TFT-LCD panel to turn on. The second power VEEG is adapted for providing a voltage level to a gate driving circuit 13 for controlling each row of pixels in the TFT-LCD panel to turn off. A delay circuit 12 is coupled between the power supply 11 and the gate driving circuit 13, and is composed of resistors R1 through R4, TFTs Q1 and Q2, and a capacitor C. The delay circuit 12 is adapted for delaying the first power VDDG for a certain input timing, and thereafter providing the same to the gate driving circuit 13 for use.
FIG. 2 is a power timing chart illustrating the powers VDDG and VEEG received by the gate driving circuit 13 as shown in FIG. 1. Referring to FIGS. 1 and 2 together, when the power supply 11 simultaneously outputs the first power VDDG and the second power VEEG, the delay circuit 12 directly provides the second power VEEG to the gate driving circuit 13 for use, i.e., the second power VEEG is not delayed thereby. In addition, the second voltage VEEG is being divided by the resistors R1 and R2 and then to charge the capacitor C until the TFT Q1 is turned on. Then, after the TFT Q1 is turned on, the TFT Q2 is turned on accordingly. Thus, the first power VDDG is provided to the gate driving circuit 13 for use.
In accordance with above description, the gate driving circuit 13 receives the second power VEEG firstly and receives the first power VDDG thereafter, by which the conventional approach employs the delay circuit 12 for avoiding the first power VDDG to be provided prior to the second power VEEG so as to prevent the gate driving circuit 13 from being suddenly burned. However, although the delay circuit 12 is workable, the employment of which has increased production cost and destroyed competence of the products.
Further, other delay circuits 12 are also proposed by engineers in the art. For example, U.S. Pat. No. 6,373,479 discloses a “Power supply apparatus of an LCD and voltage sequence control method”, in which one TFT and two resistors are disposed between the gate driving circuit and the power supply apparatus, so as to prevent the gate driving circuit 13 from being suddenly burned. Furthermore, in similar manner, U.S. Pat. No. 7,015,904 discloses a “Power sequence apparatus for device driving circuit and its method”, and U.S. patent publication No. 2006/0092883 discloses a “Power sequence apparatus and driving method thereof”.
However, all of the above mentioned technologies emphasized on protecting the gate driving circuit. They are incapable to minimizing the size of the product using the gate driving circuit. Also, they require extra power supplies or power sources, which add production cost. Further, the most important role is the foregoing technologies are not suitable for integrating with the gate driver as a gate driving circuit or designing the gate driver on a chipset.